1. Field of the Invention
The present invention relates to electrical circuits, and in particular to a thermostat circuit with an output that indicates when the circuit""s temperature is above or below a certain predetermined value.
2. Description of the Related Art
FIG. 1xe2x80x94Prior Art
FIG. 1 shows a block diagram of a prior art thermostat circuit 100. Thermostat circuit 100 comprises a constant voltage generator 105, a proportional to absolute temperature (xe2x80x9cPTATxe2x80x9d) voltage generator 110, and a current comparator 115. The constant voltage generator 105 generates a reference voltage VREF which is fed into the comparator 115. Similarly, the PTAT voltage generator 110 generates a PTAT voltage VPTAT which is fed into the comparator 115. When VPTAT greater than VREF, the output 120 is one logic state. When VREF greater than VPTAT, the output 120 is a different logic state.
Because VPTAT is proportional to temperature, this prior art thermostat circuit indicates when the circuit""s temperature is above or below a certain temperature. VREF is set to equal VPTAT at this temperature.
There are at least two disadvantages associated with the circuit of FIG. 1: (i) it will not function properly for very low supply voltages, and (ii) it requires a separate constant value as a reference. In addition, it is always desirable to have a thermostat circuit with better temperature sensitivity.
FIG. 2xe2x80x94Prior Art
FIG. 2 shows a prior art PTAT current generator. This circuit is built with current sources I1-I2, npn bipolar junction transistors Q1-Q2, resistor R1, and operational amplifier (xe2x80x9copampxe2x80x9d) A1. Opamp A1 has a noninverting input terminal (node n1), an inverting input terminal (node n2), and an output terminal (node n3).
Current sources I1-I2 are implemented so that each current source produces a substantially equal current IPTAT. This can be done, for example, by utilizing PMOS transistors. In such an implementation, the sources of the PMOS transistors are connected to Vcc, and the gates of the PMOS transistors are connected together in a current mirror configuration to node n3.
Transistor Q2 is N times larger in size than transistor Q1. Initially, with Q2 larger than Q1, and equal current from I1-I2, the voltage across Q1 will be N times larger than the voltage across Q2. Thus, node n2 will be driven higher than node n1. This will cause the voltage at node n3 to decrease. Decreasing the voltage at node n3 causes current IPTAT from current sources I1-I2 to increase. Current IPTAT will increase until the voltage across resistor R1 balances the voltage difference between transistors Q1 and Q2.
The voltage difference between transistors Q1 and Q2 is proportional to absolute temperature, and can be expressed as:                               Δ          ⁢                      xe2x80x83                    ⁢                      V            BE                          =                              kT            q                    ·                      ln            ⁡                          (              N              )                                                          (        1        )            
The current IPTAT is determined by a PTAT voltage drop on the resistor R1:                               I          PTAT                =                                            Δ              ⁢                              xe2x80x83                            ⁢                              V                BE                                                    R              1                                ·                      kT                          q              ·                              R                1                                              ·                      ln            ⁡                          (              N              )                                                          (        2        )            
FIG. 3xe2x80x94Prior Art
FIG. 3 shows a prior art VBE current generator. This circuit is built with current sources I3-I4, npn bipolar junction transistor Q3, resistor R2, and opamp A2. Opamp A2 has a noninverting input terminal (node n11), an inverting input terminal (node n12), and an output terminal (node n13).
Current sources I3-I4 are implemented so that each current source produces a substantially equal current IVBE. This can be done, for example, by utilizing PMOS transistors, as described above with respect to current sources I1-I2.
Because current sources I3-I4 produce a substantially equal current IVBE, the voltage across transistor Q3 appears across resistor R2. Therefore, the current IVBE is given by:                               I          VBE                =                              V                          BE              1                                            R            2                                              (        3        )            
In accordance with the present invention, a thermostat circuit is provided which (i) works properly with very low supply voltages, (ii) does not need a separate constant value as a reference, and (iii) has improved temperature sensitivity.
In accordance with the present invention, as illustrated in FIG. 4, current IPTAT from the prior art PTAT current generator and current IVBE from the prior art VBE current generator are fed into a current comparator. When IVBE greater than IPTAT, the output is one logic state (either high or low). When IPTAT greater than IVBE, the output is a different logic state (either low or high).
Another aspect of the present invention is the implementation of the IPTAT and IVBE current generators. One implementation shown in FIGS. 5 and 8 uses only substrate pnp bipolar devices, which are the bipolar devices usually available in CMOS technology. Using only substrate pnp bipolar devices has the additional advantage of an operating supply voltage that could be below 1 V.
Another implementation is shown in FIGS. 6 and 9 which has improved power supply rejection. Improved power supply rejection is obtained by cascoding current source transistors M1 and M2 using cascode transistors M5 and M6. And yet another implementation shown in FIGS. 7 and 8 includes a secondary loop for biasing cascode transistors M1 and M2 properly when the voltage between nodes n11 and n12 is not IVBE.
Another aspect in accordance with the present invention is the implementation of a current comparator. In one embodiment shown in FIG. 11, the current comparator is implemented so as to enable a hysteresis behavior.
Another aspect in accordance with the present invention is a circuit shown in FIG. 12 which can be used in order to test or tune a low-voltage thermostat circuit in accordance with the present invention at room temperature.